The present invention relates generally to nonvolatile memory devices and more specifically to a Flash EEPROM memory design utilizing a novel NOR-gate transistor array architecture.
Most computers currently use magnetic disk drives for data storage. However, disk drives tend to be bulky and have a number of moving parts. Consequently, they are prone to reliability problems and consume a significant amount of power. Moreover, as PC's and other digital devices such as cameras and PDA's become smaller and smaller, magnetic disk drive storage becomes even more impractical.
Recently, Flash electrically erasable programmable read-only memory (EEPROM) has emerged as a new source of nonvolatile memory storage. Flash EEPROM memory devices typically comprise an array of floating gate transistors for storing data in digital form.
FIG. 1 illustrates the cross-section of a typical NMOS floating gate transistor cell 100 used in Flash EEPROM devices. NMOS transistor cell 100 typically comprises a p-type substrate 102 having a drain region 104 and a source region 106. Drain region 104 and source region 106 typically consist of N+ diffusion regions within p-type substrate 102. A channel region 108 in substrate 102 separates drain region 104 from source region 108.
Positioned above substrate 102 and drain and source regions 104, 106 are a floating gate 110 and a control gate 112, both which typically are formed of polysilicon. Floating gate 110 is separated from substrate 102 by a thin dielectric layer 114, which in most cases, comprises silicon dioxide. Similarly, a dielectric layer 116 separates floating gate 110 and control gate 112. The entire structure is overlaid by an oxide insulating layer 118, and means are provided for applying a source voltage V.sub.S through oxide layer 118 to source region 106, a gate voltage V.sub.G to control gate 112, and a drain voltage V.sub.D through oxide layer 118 to drain region 104.
To program Flash EEPROM transistor cell 100, drain 104 and control gate 112 are raised to voltage potentials above the voltage potential of source 106. For example, drain 104 is raised to a potential V.sub.D of about 5 volts and control gate 112 is raised to a potential V.sub.G of about 12 volts. Source 106 is typically grounded. As illustrated in FIG. 1, under such conditions, the current generates hot electrons which become trapped in floating gate 110. This electron injection increases the floating gate threshold by about 3 to 5 volts.
To erase the Flash EEPROM transistor cell 100, drain 104 is typically floated, control gate 112 is grounded and a voltage of about 9 to 12 volts is applied to source 106 for a few milliseconds. As a result, the electrons stored on the floating gate 110 will tunnel through dielectric 114 to drain 104.
Finally, to read cell 100 (i.e., to determine whether a one or a zero is stored in the cell), source 106 is typically held at: ground potential and a voltage of about 5 volts is applied to control gate 112. A potential of about 1 to 2 volts is applied to drain 104. Under these conditions, an unprogrammed cell (i.e., no electrons on the floating gate) conducts a current of about 25 to 50 microamps. A programmed cell does not conduct.
As illustrated in FIG. 2, a typical Flash EEPROM array 200 comprises a plurality of transistors 202 arranged in rows and columns. In accordance with this well known arrangement, the drains D of each cell 202 in a column are connected to a common bit line 204. Similarly, the control gates of each cell 202 in each row are connected to a common word line 206. The source lines of all the cells 202 in the entire array are tied to a common source line 208.
With this configuration, cells 202 of array 200 may be individually programmed, but all the cells in array 200 are erased simultaneously because the sources of all the cells are tied together. Thus, to re-program any portion of the array, the entire array first must be erased and then re-programmed. If some of the information stored in the array is to remain the same, that information must be saved in memory during the erase process and then re-programmed back into the array. As one skilled in the art can appreciate, a complex control and memory system is needed to program this type of Flash EEPROM array.
Various different Flash EEPROM array designs have been developed to overcome some of the problems associated with having to erase an entire memory array before re-programming it. For example, NAND-gate transistor Flash EEPROM designs have been developed to overcome some of the large block erasing problems associated with the NOR-gate designs. See, for example, "An Experimental 4-Mbit CMOS EEPROM with a NAND-Structured Cell," M. Momodomi, et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1238-1243, and "A High-Density NAND EEPROM with Block-Page Programming for Microcomputer Applications," Y. Iwata, et al., IEEE Journal of Solid-State Circuits, vol. 25, No. 2, April 1990, pp. 417-424. However, while these NAND-gate transistor designs allow for smaller sector sizes and, thus, smaller block erasures, they also tend to have more overhead, causing much slower processing speeds.
Thus, a NOR-gate Flash EEPROM design which permits easy erasing and programming control of smaller transistor sectors and blocks is needed which overcomes the shortcomings of the prior art.